`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/02 14:52:16
// Design Name: 
// Module Name: alu
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module alu(
	input wire[31:0] a,b,
	input wire[4:0] c,  //sa instr[10:6]
	input wire[7:0] op,
	output wire[31:0] y,
	output wire[3:0] mul_div_control,
	output wire[3:0] memwriteALU,
	output wire addre_exception,
	output wire overflow, //reg
	output wire zero
    );

    wire[31:0] goltic;  //逻辑运算结果
    reg[5:0] star;     //0位表示的是逻辑运算单元是否运行
    wire[31:0] shiftt;   //shift_ans;
    wire[31:0] acc0,acchi,acclo;
    //wire[3:0] memwriteALU;
    //wire addre_exception;
    //wrie[31:0] Vaddress
    logict lo(a,b,star[0],op[3:0],goltic);   //逻辑运算单元
    shift shif(a,b,c,star[1],op[3:0],shiftt);  //移位单元 
    arithmetic acc(a,b,star[3],op[3:0],acc0,mul_div_control,overflow); //算术运算单元,acc为普通运算结果，acchi,acclo为乘除法运算结果。
    s_linst slinst(a,b,star[5],op[3:0],Vaddress,memwriteALU,addre_exception);   
    always @(*) begin
        star<=4'b0000; 
        case(op[7:4])
            4'b0001: star <= 6'b000001;
            4'b0010: star <= 6'b000010;
            4'b0100: star <= 6'b001000;
            4'b0101: star <= 6'b100000;
            default: star<=000000;
        endcase
    end
    assign y=star[0]? goltic:                   //star[0] 1: 逻辑运算结果
                      star[1]? shiftt:          //star[1] 1： 移位结果
                      star[3]? acc0:            //star[3] 1：运算结果
                      star[5]? Vaddress:32'b0;   //star[5] 1：存取地址                 
    assign zero = (y==32'b0);
    
endmodule




